Utmel: An Overview of Deserializers’ Working Principles and Architectural Variations

Deserialization is the process of converting data that has been stored or transported in a format other than its original format back into its original format.

A deserializer is a device or software component that converts serialized data into its original format.

A deserializer is a device or software component that converts serialized data into its original format.

SHENZHEN, GUANGDONG, CHINA, April 3, 2023/EINPresswire.com/ — Deserialization is the process of converting data that has been stored or transported in a format other than its original format back into its original format. It is the reverse process of serialization which is used to convert an object into a format that can be stored or transmitted.

For example, when data is sent over a network or stored in a file, it is often serialized into a binary format that can be transmitted or stored more efficiently. When this data is received or retrieved, it needs to be deserialized back into its original format so that it can be used by the application.

What is a Deserializer?

A deserializer is a device or software component that converts serialized data into its original format. In serialization, an object or data structure is converted into a format that can be stored or transmitted, such as a byte stream. Deserialization is the process of converting that serialized data back into its original format, so that it can be used by a program or application. Deserializers are often used in communication protocols, where data is transmitted over a network or between different systems in a serialized format, and needs to be deserialized at the receiving end to be processed.

For example, the DS90UB914ATRHSTQ1 is a 25-100MHz 10/12-Bit FPD-Link III Deserializer. It is designed to interface with FPD-Link III serializers and is used to convert serialized data back into parallel data. It comes in a WQFN (RHS) package with 48 pins.

How Does a Serializer/Deserializer Work?

A deserializer works by taking in a serial data stream, which is a single stream of data bits, and using a clock signal to extract the individual bits and group them together into their original parallel form.

The clock signal provides the timing information needed to correctly extract the bits and group them together. The deserializer uses this clock signal to synchronize its internal circuits with the incoming data stream, so that the bits are extracted at the correct rate and grouped together into the correct parallel format.

Once the bits have been extracted and grouped together, the deserializer outputs them as a parallel data stream, which can then be further processed by other electronic components. Deserializers are commonly used in applications such as high-speed data communication, video processing, and digital signal processing, where data is transmitted in serial form over a communication channel, but needs to be processed in parallel form by the receiving system.

What are the Architectures of Deserializer?

There are several architectures of deserializers, but one common architecture is the parallel-in serial-out (PISO) shift register. In this architecture, the deserializer consists of a set of parallel input lines that receive the serialized data and a clock input that synchronizes the operation of the shift register. The data is then loaded into the shift register one bit at a time, using the clock signal to control the timing of the data loading. Once all the bits have been loaded into the shift register, the data is available on a single serial output line.

Another common architecture is the successive approximation register (SAR) deserializer. This architecture uses a binary search algorithm to determine the value of each bit in the serial data stream. The SAR deserializer operates by sampling the input signal at a high frequency and comparing each sample to a voltage reference. The result of each comparison is stored in a register, and the register is shifted one bit at a time to produce the output data.

There are also hybrid deserializer architectures that combine elements of the PISO and SAR architectures to achieve high-speed and high-accuracy data recovery. These architectures typically use multiple stages of PISO and SAR circuits to provide the necessary data processing and filtering for high-performance applications.

Click Here to get more details about Deserializers.

Gloria
Utmel Electronic Limited
+86 13728988459
info@utmel.com
Visit us on social media:
Facebook
Twitter
LinkedIn